Semiconductor device and method manufacturing the same, circuit board, and electronic instrument

ABSTRACT

A semiconductor device comprises a plurality of semiconductor chips ( 20, 30 ) having electrodes ( 22, 32 ) and aligned in the horizontal direction; a substrate ( 10 ) on which is formed an interconnect pattern ( 12 ) having bonding portions ( 14 ) connected to the electrodes ( 22, 32 ) of the semiconductor chips ( 20, 30 ) and lands ( 16 ) connected to the bonding portions ( 14 ), and external electrodes ( 40 ) provided on the lands ( 16 ) and connected to the electrodes ( 22, 32 ) through an interconnect pattern ( 12 ).

This application is a 371 of PCT/JP99/04785, filed Sep. 3, 1999

TECHNICAL FIELD

The present invention relates to a semiconductor device and method ofmanufacturing the same, to a circuit board and to an electronicinstrument.

BACKGROUND OF ART

In recent years, with the increasing compactness of electronicinstruments, the development of multichip modules incorporating aplurality of semiconductor chips at high density is proceeding. With amultichip module, since an existing plurality of semiconductor chips canbe used, the cost can be reduced compared with the design of a newintegrated circuit.

However, conventional multichip modules have used wire bonding toconnect interconnect pattern of a substrate to the electrodes of thesemiconductor chip. As a result, the interconnect pattern requiresbonding pads for the wires, and therefore the area of the substrate isincreased, preventing the required compactness of the package from beingfully achieved.

The present invention solves this problems, and has as its object theprovision of a compact semiconductor device incorporating a plurality ofsemiconductor chips at high density and a method of manufacturing thesame, of a circuit board and of an electronic instrument.

DISCLOSURE OF INVENTION

(1) A semiconductor device of the present invention comprises:

a plurality of semiconductor chips having electrodes, and aligned in ahorizontal direction for face-down bonding;

a substrate on which an interconnect pattern is formed, the interconnectpattern having bonding portions to which the electrodes of thesemiconductor chip are connected, and lands to which the bondingportions are electrically connected; and

external electrodes provided on the lands.

According to this aspect of the present invention, a plurality ofsemiconductor chips is aligned in a horizontal direction and mounted ona substrate. Each semiconductor chip is subjected to face-down bonding.Since the bonding is carried out within the region where thesemiconductor chip is mounted, the area of the substrate can be kept tothe minimum required. As a result, the semiconductor device can be mademore compact.

(2) In the semiconductor device:

the external electrodes may be disposed within mounting regions of thesemiconductor chips.

By means of this, external electrodes can be provided corresponding tothe electrodes of the semiconductor chip, within the region where eachsemiconductor chip is mounted.

(3) In the semiconductor device:

the external electrodes may be disposed outside regions where thesemiconductor chips are mounted.

By means of this, the external electrodes can be aligned on theperiphery of the substrate.

(4) In the semiconductor device:

the substrate may be a flexible substrate and is formed to be largerthan the regions where the semiconductor chips are mounted, and a flatsupport member may be provided on a periphery of the substrate.

By means of this, even if a flexible substrate is used, the uniformheight (coplanarity) of the external electrodes can be assured by meansof the flat support member.

(5) In the semiconductor device:

the external electrodes may be disposed within a region where any one ofthe semiconductor chips is mounted.

By means of this, all of the external electrodes can be provided withinthe region where any one of the semiconductor chips is mounted, and noexternal electrodes can be provided within the region where any othersemiconductor chip is mounted.

(6) In the semiconductor device:

the substrate may be a flexible substrate and part of the substrate isbent; and

a surface of the one semiconductor chip, which is disposed at a regionwhere the external electrodes are provided, opposite to a surface onwhich the electrodes are formed may be adhered to a surface of at leastone remaining semiconductor chip opposite to a surface on which theelectrodes are formed.

Since on the semiconductor chip another semiconductor chip is adhered,the size of the semiconductor device in the horizontal direction can bereduced.

(7) In the semiconductor device:

the substrate may have at least one hole formed along a region to bebent.

By forming the hole in the substrate, the resilience of the substratecan be reduced, and the bent state can be more easily maintained.

(8) In the semiconductor device:

the hole may be a slot extending along a bending line;

the interconnect pattern may be formed to pass over the hole; and

an edge of the slot extending along the bending line may form a part ofan outer edge.

Since a part of the outer edge of the semiconductor device is formed byan edge of the slot, the edge of the semiconductor device can bepositioned accurately.

(9) In the semiconductor device:

a plurality of the holes may be formed;

the interconnect pattern may be formed to pass over the plurality ofholes; and

the plurality of holes may be slots extending along a bending line, andare aligned.

By means of this, the substrate may be made easier to bend. (10) In thesemiconductor device:

the substrate may have a slit formed along a region to be bent; and

the substrate may be divided by the slit, and a gap may be opened upbetween opposing divided edges.

When the divided substrate is considered as a whole, it can be bent moreeasily.

(11) In the semiconductor device:

a joining member may be provided spanning the slit.

By means of this, the bent portion of the substrate can be supported bythe joining member.

(12) In the semiconductor device:

a flexible resin may be provided on the interconnect pattern in thehole; and

the resin may be bent together with the substrate.

By means of this, the bent portion of the substrate can be supported bythe resin.

(13) In the semiconductor device:

the semiconductor chips may be adhered by an electrically conductiveadhesive or a thermally conductive adhesive.

When an electrically conductive adhesive is used, the electricalpotential of the adhering surfaces of the semiconductor chips can bemade the same. When a thermally conductive adhesive is used, cooling canbe achieved by passing heat from the semiconductor chip which emits moreheat to the semiconductor chip which emits less heat.

(14) In the semiconductor device:

a surface area of one of the semiconductor chips may be larger than asurface area of a remaining semiconductor chip; and

the external electrodes may be formed only in a region where thesemiconductor chip having a larger surface area is provided.

By means of this, the largest possible region for providing the externalelectrodes can be assured, without going outside the surface area of thesemiconductor chip.

(15) In the semiconductor device:

the electrodes of the semiconductor chips may be connected to thebonding portions by an anisotropically conductive material includingconductive particles dispersed in an adhesive.

Since the bonding portions and electrodes are electrically connected bythe anisotropically conductive material, a semiconductor device can bemanufactured by a method of outstanding reliability and productivity.

(16) A method of manufacturing a semiconductor device of the presentinvention comprises:

a step of providing a substrate on which an interconnect pattern isformed, the interconnect pattern having a plurality of bonding portionsand a plurality of lands electrically connected to the bonding portions,and providing a plurality of semiconductor chips having electrodes;

a step of providing anisotropically conductive materials includingconductive particles dispersed in an adhesive at least on the bondingportions;

a step of positioning the electrodes over the bonding portions on theanisotropically conductive materials, and mounting the semiconductorchips over the substrate;

a step of applying pressure to at least one of the semiconductor chipsand the substrate so that the bonding portions and the electrodes areelectrically connected by the conductive particles; and

a step of forming external electrodes on the lands.

According to this aspect of the present invention, a plurality ofsemiconductor chips is mounted on the substrate, and the electrodes ofthe semiconductor chips and bonding portions are subjected to face-downbonding. Therefore, since the bonding is carried out within the regionwhere the semiconductor chip is mounted, the area of the substrate canbe kept to the minimum required. As a result, the semiconductor devicecan be made more compact.

Since the bonding portions and electrodes are electrically connected bythe anisotropically conductive material, a semiconductor device can bemanufactured by a method of outstanding reliability and productivity.

(17) In this method,

the substrate may be a flexible substrate and formed to be larger thanthe regions where the semiconductor chips are mounted; and

a flat support member may be provided on a periphery of the substrate.

By means of this, even if a flexible substrate is used, the uniformheight (coplanarity) of the external electrodes can be assured. In thecase where all of the external electrodes are provided outside theregion where all of the semiconductor chips are mounted, the externalelectrodes can be provided on the region to which the flat supportmember is attached.

(18) The method may further comprise a step of bending a part of thesubstrate, after the step of mounting the semiconductor chips on thesubstrate, so that a surface of one of the semiconductor chips oppositeto a surface where the electrodes are provided is adhered to a surfaceof another of the semiconductor chips opposite to a surface on which theelectrodes are formed.

Since on the semiconductor chip another semiconductor chip is adhered,the size of the semiconductor device in the horizontal direction can bereduced.

(19) In this method,

the substrate may have at least one hole formed along a region to bebent.

In this way, by forming a hole in the substrate, the resilience of thesubstrate can be reduced, and the substrate can be made easier to bend.

(20) The circuit board of the present invention has the above describedsemiconductor device mounted.

(21) The electronic instrument of the present invention has the abovedescribed circuit board.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C show a first embodiment of the semiconductor device towhich the present invention is applied;

FIGS. 2A to 2C show a second embodiment of the semiconductor device towhich the present invention is applied;

FIGS. 3A to 3C show a third embodiment of the semiconductor device towhich the present invention is applied;

FIG. 4 shows a modification of the third embodiment to which the presentinvention is applied;

FIG. 5 shows a fourth embodiment of the semiconductor device to whichthe present invention is applied;

FIGS. 6A to 6C show a development of a fourth embodiment of thesemiconductor device to which the present invention is applied;

FIG. 7 shows a development of a fifth embodiment of the semiconductordevice to which the present invention is applied;

FIG. 8 shows a development of a sixth embodiment of the semiconductordevice to which the present invention is applied;

FIG. 9 shows a development of a seventh embodiment of the semiconductordevice to which the present invention is applied;

FIG. 10 shows an eighth embodiment of the semiconductor device to whichthe present invention is applied;

FIG. 11 shows a ninth embodiment of the semiconductor device to whichthe present invention is applied;

FIG. 12 shows a circuit board on which the semiconductor device of thisembodiment is mounted;

FIG. 13 shows an electronic instrument having a circuit board on whichthe semiconductor device of this embodiment is mounte.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention is now described in terms of a number of preferredembodiments, with reference to the drawings.

First Embodiment

FIGS. 1A to 1C show a first embodiment of the semiconductor device towhich the present invention is applied. It should be noted that FIG. 1Ais a plan view of the semiconductor device, FIG. 1B is a cross-sectionalview along the line IB—IB in FIG. 1A, and FIG. 1C is a bottom view ofthe semiconductor device. A semiconductor device 1 comprises a substrate10 a plurality (for example two) of semiconductor chips 20 and 30, and aplurality of external electrodes 40.

The substrate 10 may be formed of either of an organic or inorganicmaterial, or may be a compound construction thereof. As a substrate 10formed of an organic material may be cited, for example, a flexiblesubstrate formed of a polyimide resin. As a substrate 10 formed of aninorganic material may be cited, for example, a ceramic substrate orglass substrate. As a compound construction of organic and inorganicmaterials may be cited, for example, a glass epoxy substrate.

On the substrate 10, is formed an interconnect pattern 12. Theinterconnect pattern 12 is formed on one surface of the substrate 10. Itshould be noted that in addition to the interconnect pattern 12 formedon the one surface of the substrate 10, an interconnect pattern may alsobe formed on the other surface.

The interconnect pattern 12 can be formed by covering the substrate 10with copper or the like by sputtering or the like to form a conductivefilm, and etching the same. In this case, the interconnect pattern 12 isformed directly on the substrate 10, and forms a two-layer substratewithout an intervening adhesive. Alternatively, a three-layer substratemay be used with an adhesive interposed between the substrate 10 and theinterconnect pattern 12. Alternatively, a built-up substrate ofmulti-layer construction may be used, with an insulating resin andinterconnect pattern laminated on the substrate, or a multi-layersubstrate with a plurality of substrates laminated may be used.

The interconnect pattern 12 includes a plurality of bonding portions 14and a plurality of lands 16. Each of the bonding portions 14 iselectrically connected to at least one of the lands 16. The bondingportions 14 and lands 16 are formed to be larger in area than theinterconnect portions. It should be noted that bumps may be formed onthe bonding portions 14.

The bonding portions 14 and lands 16 are formed within the mountingregion of each of the semiconductor chips 20 and 30 on the substrate 10,and are not formed outside these regions. The bonding portions 14positioned within the mounting regions of each of the semiconductorchips 20 and 30 are connected to the lands 16 positioned within therespective mounting region. Alternatively, bonding portions 14positioned within the mounting region of either one of the semiconductorchips 20 and 30 may be connected to lands 16 positioned within themounting region of the other of the semiconductor chips 20 and 30. Tosimplify trimming die, the substrate 10 may be formed to be oblong asshown in the drawing, and where even more extreme compactness isrequired, may be formed along the outline of the semiconductor chip.

In the substrate 10 are formed through holes 18. On the through holes 18are positioned the lands 16. That is to say, the lands 16 are able to beconnected to the surface opposite to the surface of formation of theinterconnect pattern 12 through the through holes 18. In this way, onthe surface of the substrate 10 opposite to the surface where theinterconnect pattern 12 is formed, a plurality of external electrodes 40(see FIG. 1C) electrically connected to the interconnect pattern 12 canbe formed.

The plurality of semiconductor chips 20 and 30 are, for example, flashmemory and SRAM, both SRAMs, both DRAMs, memory and ASIC, or an MPU andmemory, and have respective pluralities of electrodes 22 and 32. Theelectrodes 22 and 32 are positioned 20 over some of the bonding portions14, and are electrically connected through an anisotropically conductivematerial 50. That is to say, the semiconductor chips 20 and 30 aresubjected to face-down bonding to the interconnect pattern 12 of thesubstrate 10 by facing down the surfaces on which the electrodes 25 22and 32 are formed. It should be noted that the semiconductor chips 20and 30 shown in the drawings have different sizes and shapes, but theymay equally be of the same size and shape. The electrodes 22 and 32 arecommonly gold formed by plating or as wire, but may equally be nickel,solder or suchlike material.

The anisotropically conductive material 50 comprises an adhesive(binder) in which conductive particles (conductive filler) is dispersed,and may also include a dispersant. The anisotropically conductivematerial 50 may be preformed into a sheet, then adhered to the substrate10, or may be disposed in liquid form on the substrate 10. Athermosetting adhesive is commonly used as the adhesive of theanisotropically conductive material 50. The anisotropically conductivematerial 50 is provided at least on the bonding portions 14.Alternatively, when the anisotropically conductive material 50 isprovided to cover the whole of the substrate 10, this step can becarried out simply. When the anisotropically conductive material 50 isprovided to exclude the periphery of the substrate 10, theanisotropically conductive material 50 will not be attached to theperipheral surface of the substrate 10, which is convenient for thelater handling of the substrate 10.

The anisotropically conductive material 50 is squeezed between theelectrodes 22 and 32 and the bonding portions 14, and the conductiveparticles are arranged to provide electrical conduction therebetween. Inthis embodiment, the semiconductor chips 20 and 30 are subject toface-down bonding. When the face-down bonding is performed, instead ofusing the anisotropically conductive material 50, any of at least one oflight, heat, pressure, and vibration may be used to bond the electrodes22 and 32 to the bonding portions 14. In this case, the reliability ishighest with metal-to-metal bonding. In this case, between thesemiconductor chips 20 and 30 and the substrate 10 is commonly filledwith an underfill resin.

The external electrodes 40 are;provided on lands 16 of the interconnectpattern 12. In more detail, the external electrodes 40 are provided onthe surface opposite to the surface where the interconnect pattern 12 isformed on the substrate 10, and are electrically connected to the lands16 through the through holes 18. The electrical connection of theexternal electrodes 40 to the lands 16 is commonly achieved by providingsolder balls together with flux on the through holes on the surface ofthe substrate opposite to that on which the semiconductor chips aremounted, and formed by a reflow process, but may equally be achieved byproviding a conductive material such as gold or copper plated on theinner surface of the through holes 18. Alternatively, when solder ballsare used as the external electrodes 40, the through holes 18 may befilled with the solder which is the material of the solder balls, and aconductive material formed integrally with the solder balls within thethrough holes 18.

Further, on the surface opposite to the semiconductor chip mountingsurface, may be formed lands for external electrodes connected by viaholes or through holes to the interconnect pattern 12, and externalelectrodes may be formed thereon. The external electrodes may equally beformed of a metal other than the solder described above, or of aconductive resin, or the like.

As described above, when all of the lands 16 are positioned within themounting region of the semiconductor chips 20 and 30, the externalelectrodes 40 are also positioned within the mounting region of thesemiconductor chips 20 and 30 (FAN-IN structure). When bonding portions14 provided within the mounting region of some of the semiconductorchips 20 and 30 are connected to lands 16 provided within the mountingregion, the external electrodes 40 are also electrically connected toelectrodes 22 and 32 of semiconductor chips 20 and 30 corresponding tothe mounting region in which the external electrodes 40 are provided.

According to this embodiment, the plurality of semiconductor chips 20and 30 are aligned in the horizontal direction and mounted on thesubstrate 10, and the electrodes 22 and 32 of the semiconductor chips 20and 30 are subjected to face-down bonding to the bonding portions 14.Therefore, since bonding is carried out within the region of thesemiconductor chips 20 and 30, the area of the substrate 10 can be keptto the minimum required. As a result, the semiconductor device 1 can bemade compact.

This embodiment has the above described construction, and one example ofa method of manufacturing the same is now described. First, thesubstrate 10 having formed thereon the interconnect pattern 12 which hasa plurality of bonding portions 14 and a plurality of lands 16 connectedto the bonding portions 14 is provided in advance. Then on the surfaceof the substrate 10 on which the interconnect pattern 12 is formed, theanisotropically conductive material 50 is provided. In more detail, theanisotropically conductive material 50 is provided on at least thebonding portions 14.

The plurality of the semiconductor chips 20 and 30 having a plurality ofelectrodes 22 and 32 is provided in advance. The electrodes 22 and 32are positioned over the bonding portions 14 of the anisotropicallyconductive material 50, and the semiconductor chips 20 and 30 aremounted on the substrate 10.

Next, at least one of the semiconductor chips 20 and 30 and thesubstrate 10 is pressed, and the bonding portions 14 and the electrodes22 and 32 are electrically connected through the conductive particles ofthe anisotropically conductive material 50.

Then from the surface of the substrate 10 opposite to that on which theinterconnect pattern 12 is formed, with through holes 18 interposed, theexternal electrodes 40 are formed on the lands 16.

By the above process, the semiconductor device 1 is obtained. Accordingto this embodiment, since the bonding portions 14 and electrodes 22 and32 are electrically connected by the anisotropically conductive material50, a semiconductor device 1 can be manufactured by a method ofoutstanding reliability and manufacturing characteristics.

Second Embodiment

FIGS. 2A to 2C shows a second embodiment of the semiconductor device towhich the present invention is applied. It should be noted that FIG. 2Ais a plan view of the semiconductor device, FIG. 2B is a cross-sectionalview along the line IIB—IIB in FIG. 2A, and FIG. 2C is a bottom view ofthe semiconductor device. A semiconductor device 2 includes a substrate110, external electrodes 140, and the plurality (for example, two) ofsemiconductor chips 20 and 30 used in the first embodiment.

On the substrate 110 is formed an interconnect pattern 112. Theinterconnect pattern 112 includes bonding portions 114 and lands 116.The bonding portions 114 are provided in positions corresponding to theelectrodes 22 and 32 of the semiconductor chips 20 and 30. On the otherhand, the lands 116 are formed only within the mounting region of one ofthe semiconductor chips 20 and 30. Therefore, the lands 116 within thisone of the mounting regions are electrically connected to the bondingportions 114 within the other of the mounting regions throughinterconnects 115.

Since the lands 116 are formed in this way, the external electrodes 140are also formed only within the mounting region of one of thesemiconductor chips 20 and 30. It should be noted that in FIG. 2C, forsimplification a. reduced number of the external electrodes 140 areshown, and a larger number of the external electrodes 140 can actuallybe provided.

Other than this, the structure and method of manufacture is the same asin the first embodiment described above. Depending on the interconnectpattern of the mounting substrate or motherboard, it may be beneficialfor all of the external electrodes 140 to be concentrated in a singlelocation as in the second embodiment of the semiconductor device 2.

To prevent inclination of the semiconductor device due to a weightimbalance during mounting on the motherboard, a projection of the samesize, height, and form as the external electrodes 140 may be formed onthe surface of the substrate 110 opposite to that on which thesemiconductor chip 20 is mounted. This projection may be formed of resinor tape or the like.

Third Embodiment

FIGS. 3A to 3C show a third embodiment of the semiconductor device towhich the present invention is applied. It should be noted that FIG. 3Ais a plan view of the semiconductor device, FIG. 3B is a cross-sectionalview along the line IIIB—IIIB in FIG. 3A, and FIG. 3C is a bottom viewof the semiconductor device. A semiconductor device 3 includes asubstrate 210, external electrodes 240, and the plurality (for example,two) of semiconductor chips 20 and 30 used in the first embodiment.

On the substrate 210 is formed an interconnect pattern 212. Theinterconnect pattern 212 includes bonding portions 214 and lands 216.The bonding portions 214 are provided in positions corresponding to theelectrodes 22 and 32 of the semiconductor chips 20 and 30. On the otherhand, the lands 216 are formed on the outside of the mounting region ofthe semiconductor chips 20 and 30. Therefore, the bonding portions 214within the mounting region of the semiconductor chips 20 and 30 and thelands 216 positioned outside this mounting region are electricallyconnected through interconnects 215. The substrate 210 is formed to belarger than the mounting region of the semiconductor chips 20 and 30.

Since the lands 216 are formed in this way, the external electrodes 240are also formed outside the mounting region of the semiconductor chips20 and 30 (FAN-OUT structure). It should be noted that in FIG. 3C, forsimplification a reduced number of the external electrodes 240 areshown, and in practice a larger number of the external electrodes 240can be provided.

On the substrate 210 is provided a flat support member 200 which isrigid, for example of metal. The flat support member 200 serves toreinforce the substrate 210 and maintain flatness, so that as long as itis rigid there are no restrictions on the material. For example, a metalsuch as stainless steel or a copper alloy is commonly used, but this mayalso be formed of plastic, ceramic, or another insulating material. Inthis embodiment, the anisotropically conductive material 50 is providedon the interconnect pattern 212, and when there is no conduction fromthe conductive particles of the anisotropically conductive material 50,even if a metal flat support member 200 is used, electrical conductionbetween the interconnect pattern 212 and the flat support member 200 canbe prevented. Alternatively, when the flat support member 200 is formedof an insulating material, there may be an electrical connection fromthe conductive particles of the anisotropically conductive material 50.By forming an insulation layer at least on the contact surface with theanisotropically conductive material 50 on the flat support member 200,electrical conduction between the interconnect pattern 212 and the flatsupport member 200 can be prevented even if the flat support member 200is of metal. The flat support member 200 may be adhered to the substrate210 with a general insulating adhesive other than the anisotropicallyconductive material.

The flat support member 200 is adhered outside the mounting region ofthe semiconductor chips 20 and 30 or the on the periphery of thesubstrate 210 by the anisotropically conductive material 50. Therefore,even if the substrate 210 is a flexible substrate, the flatness of theportion outside the semiconductor chips 20 and 30 and the periphery ofthe substrate 210 can be assured. In this embodiment, the flatness ofthe region of the substrate 210 in which the external electrodes 240 areprovided is assured by the flat support member 200, as a result of whichthe uniform height (coplanarity) of the external electrodes 240 can beassured. Other than this, the structure and method of manufacture is thesame as in the first embodiment described above, and description isomitted.

It should be noted that in this embodiment, in the mounting region ofthe semiconductor chips 20 and 30 on the substrate 210, no externalelectrodes 240 are provided, but in this region also, externalelectrodes may be provided (FAN-IN/OUT structure). In addition, or as analternative, external electrodes may be provided in the region betweenthe semiconductor chip 20 and the semiconductor chip 30. Thesemiconductor device 4 shown in FIG. 4 is an example showing theexternal electrodes 240 provided inside and outside of the mountingregion of the semiconductor chips 20 and 30 and between thesemiconductor chips 20 and 30 on the substrate 210.

It should be noted that in the third embodiment, when the substrate 210itself has flatness retaining properties (for example when the substrate210 is of ceramic or glass epoxy), then the flat support member 200 isnot necessarily required.

Fourth Embodiment

FIG. 5 shows a fourth embodiment of the semiconductor device to whichthe present invention is applied, and FIGS. 6A to 6C show a developmentof the substrate of the semiconductor device shown in FIG. 5. It shouldbe noted that FIG. 6A is a plan view, FIG. 6B is a cross-sectional viewalong the line VB—VB in FIG. 6A, and FIG. 6C is a bottom view. Asemiconductor device 5 includes a substrate 310, semiconductor chips 320and 330, and external electrodes 340.

The substrate 310, is as shown in FIG. 5 formed of a material which canbe bent, and in particular in the case of a two-layer flexible substrateor in the case that the interconnect density is required to be furtherincreased, a built-up. type of flexible substrate is preferable. Thesubstrate 310 forms an oblong shape, longer in one direction. At bothends of this substrate 310, the semiconductor chips 320 and 330 aremounted. It should be noted that in this embodiment the semiconductorchips 320 and 330 are of the same size and the same shape, but mayequally be of a different size or different shape.

An interconnect pattern 312 is formed on the substrate 310. Theinterconnect pattern 312 includes bonding portions 314 and lands 316.The bonding portions 314 are provided in positions corresponding toelectrodes 322 and 332 of the semiconductor chips 320 and 330, and areelectrically connected through an anisotropically conductive material350. On the other hand, the lands 316 are formed only within themounting region of one of the semiconductor chips 320 and 330. For thisreason, the lands 316 within this one mounting region and the bondingportions 314 within the other mounting region are electrically connectedthrough interconnects 315. The interconnects 315 are formed between thesemiconductor chips 320 and 330, and are not covered thereby, and areprotected by being covered by a protective layer 302 of resist or thelike.

Since the lands 316 are formed in this way, the external electrodes 340are also formed only within the mounting region of one of thesemiconductor chips 320 and 330. It should be noted that in the drawing,for simplification a reduced number of the external electrodes 340 areshown, and in practice a larger number of the external electrodes 340can be provided. With regard to the disposition of the externalelectrodes 340, as described in the third embodiment, they may equallybe disposed using a flat support member on the outside of thesemiconductor chip.

In this embodiment, the region of the substrate 310 between thesemiconductor chips 320 and 330 is bent so that the surface of thesubstrate 310 on which the semiconductor chips 320 and 330 are mountedforms a V-shape. It should be noted that in the drawing, the substrate310 is bent gradually without forming a crease, but equally thesubstrate 310 may form a crease. In the substrate 310, as shown in FIGS.6A and 6C, in the bending region at least one, or a plurality of holes300 may be formed. By this means, the resilience of the substrate 310 isreduced, and it can be more easily bent, and becomes easier to hold thebent form. It should be noted that the interconnects 315 are preferablyformed so as to avoid the holes 300, but the interconnects 315 may beformed over the holes 300.

The substrate 310 is bent, and the surface of the semiconductor chip 320opposite to the surface on which the electrodes 322 are formed, and thesurface of the semiconductor chip 330 opposite to the surface on whichthe electrodes 332 are formed are adhered by an adhesive 304. The bentform of the substrate 310 is maintained by the adhesive force of theadhesive 304. Since the surfaces of the semiconductor chips 320 and 330are flat, the adhesion is easy to achieve. When the adhesive 304 is anelectrically conductive adhesive, the potential of the adhered surfacesof the semiconductor chips 320 and 330 can be made the same. When theadhesive 304 is a thermally conductive adhesive, heat can be transferredbetween the semiconductor chips 320 and 330. For example, when one ofthe semiconductor chips 320 and 330 emits more heat and the other emitsless heat, then cooling can be achieved by passing heat from the one tothe other. The adhesive 304 may equally be a pressure-sensitiveadhesive. The adhesive 304 in sheet form or liquid form is applied tothe back surfaces of the semiconductor chips 320 and 330 in the stateshown in FIGS. 6A to 6C, and thereafter the back surfaces of the bothsemiconductor chips are adhered together. Alternatively, back surfacesof the semiconductor chip may be positioned together and then the gapfilled with the adhesive 304 in liquid form.

Except for the above described points, the construction is the same asin the first embodiment described above, and description is omitted. Itshould be noted that semiconductor chips of different sizes may be used,but in this case when the larger semiconductor chip is disposed on theside of formation of the external electrodes 340, this will give greatergeometrical stability, and is preferable.

In this embodiment, two semiconductor chips 320 and 330 are used, but aplurality of more than two semiconductor chips may also be used. In sucha case, the surface of one semiconductor chip opposite to the surface onwhich the electrodes are formed may be adhered to the surface of one ormore of the remaining plurality of semiconductor chips opposite to thesurface on which the electrodes are formed. By means of such aformation, a plurality, and in particular a large number ofsemiconductor chips can be superimposed within a small area.

Further, without bending and superimposing the substrate for each singlesemiconductor chip, a plurality of semiconductor chips may be mounted onplane, and then the substrate bent and superimposed.

In this embodiment of the semiconductor device 5, a plurality of thesemiconductor chips 320 and 330 are superimposed, and therefore evenmore compactness can. be achieved than in the previous embodiments. Itshould be noted that for the method of manufacturing the semiconductordevice 5, the same method can be applied as that described in the firstembodiment, except for the bending of the substrate 310.

Fifth Embodiment

FIG. 7 is a development of a fifth embodiment of the substrate of thesemiconductor device to which the present invention is applied. In thisembodiment of the semiconductor device also, as with the semiconductordevice 5 shown in FIG. 5, a substrate 410 is in a bent configuration. Onthe substrate 410, as in the fourth embodiment, the semiconductor chips320 and 330 are mounted.

In the substrate 410 shown in FIG. 7, at least one hole 400 is formed.The hole 400 is a slot extending along the bending line of the substrate410. In other words, the substrate 410 is bent along the hole 400 whichis a slot. In FIG. 7, a plurality of holes 400 is aligned. Since theholes 400 are formed inside a side edge of the substrate 410, an edgeportion of the substrate 410 remains. Therefore, the substrate 410remains connected without being divided apart.

On the substrate 410 an interconnect pattern 412 is formed. Theinterconnect pattern 412 is formed to pass over the holes 400. Since thesubstrate 410 is connected even with the holes 400 formed, theinterconnect pattern 412 is not divided.

When the substrate 410 of the above construction is bent as thesubstrate 310 in FIG. 5, the edge where the holes 400 are formed formspart of the outer edge of the semiconductor device. Therefore, since thesemiconductor device forms a clear outline, positioning is easy.

To other aspects of the embodiment, the description under the fourthembodiment can be applied.

Sixth Embodiment

FIG. 8 is a development of a sixth embodiment of the substrate of thesemiconductor device to which the present invention is applied. In thisembodiment of the semiconductor device also, as with the semiconductordevice 5 shown in FIG. 5, a substrate 510 is in a bent configuration. onthe substrate 510, as in the fourth embodiment, the semiconductor chips320 and 330 are mounted.

The substrate 510 shown in FIG. 8 has a slit 500 formed, whereby it isdivided. In other words, the both dividing edges of the substrate 510 isspaced apart whereby the slit 500 is formed. The slit 500. extends alongthe bending line of the substrate 510. In other words, the substrate 510is bent along the slit 500.

On the substrate 510, an interconnect pattern 512 is formed. Theinterconnect pattern 512 is formed to pass over the slit 500. Since thesubstrate 510 is divided, it is preferable for the width of theinterconnect pattern 512 to be greater than the width of theinterconnect pattern 412 shown in FIG. 7.

When the substrate 510 of the above construction is bent as thesubstrate 310 in FIG. 5, the edge where the slit 500 is formed formspart of the outer edge of the semiconductor device. Therefore, since thesemiconductor device forms a clear outline, positioning is easy.

To other aspects of the embodiment, the description under the fourthembodiment can be applied.

Seventh Embodiment

FIG. 9 is a development of a sixth embodiment of the substrate of thesemiconductor device to which the present invention is applied. Thisembodiment differs from the sixth embodiment in that a joining member620 is provided, spanning the slit 500 of the substrate 510 shown inFIG. 8. By the provision of the joining member 620, the substrate 510which has been divided is joined and reinforced. Therefore, the width ofan interconnect pattern 612 may be less than the width of theinterconnect pattern 512 shown in FIG. 8. The joining member 620 may beformed of the same material as the interconnect pattern 612. When theinterconnect pattern 612 is formed by etching of a metal foil such ascopper foil, the joining member 620 may be formed at the same time, thusnot requiring the number of processes to be increased.

To other aspects of the embodiment, the description under the sixthembodiment can be applied. In this embodiment, the joining member 610has been described spanning the slit 500 separating the substrate 510,but the joining member 610 may equally span holes 400 (see FIG. 7) whichdo not separate the substrate 510. Such holes 400 may also be termed“slits.”

Eighth Embodiment

FIG. 10 shows an eighth embodiment of the semiconductor device to whichthe present invention is applied. The semiconductor device shown in FIG.10 has the same configuration as the semiconductor device 5 shown inFIG. 5, except for a substrate 710 and hole 700.

In the substrate 710, in the region of bending, a plurality of holes 700is formed. The plurality of holes 700 comprise slots extending along thebending line, in a in a parallel formation. Alternatively, the holes 700may be termed “slits,” and in place of the holes 700, slits dividing thesubstrate 710 may be formed. By the formation of such holes (or slits)700, the substrate 710 is made easier to bend. The interconnect pattern312 passes over the holes 700. In this embodiment the descriptionreferring to FIG. 5 can also be applied.

Ninth Embodiment

FIG. 11 shows a ninth embodiment of the semiconductor device to whichthe present invention is applied. In the semiconductor device shown inFIG. 11, with a hole 800 formed in a substrate 810 interposed, aflexible resin 820 is provided on the interconnect pattern 312. As theresin 820 for example a soft polyimide resin may be used.

The hole 800 is formed in the region where the substrate 810 is bent.The hole 800 may be termed a “slit,” and in place of the hole 800, aslit dividing the substrate 810 may be formed.

In this embodiment, the interconnect pattern 312 is formed on the insideof the bent portion of the substrate 810, and therefore without theresin 820, the interconnect pattern 312 would be exposed to the exteriorthrough the hole 800. But here the provision of the resin 820 within thehole 800 enables the interconnect pattern 312 to be protected. Moreover,since the resin 820 is flexible, the resin 820 can be provided while thesubstrate 810 is still opened up in the flat state, and the substrate810 bent thereafter, improving the working efficiency. It should benoted that the description of this embodiment can also be applied to theother embodiments.

The present invention can be applied to a face-down type ofsemiconductor device or to the module construction thereof. As aface-down type semiconductor device may be cited, for example, COF (ChipOn Flex/Film) construction or COB (Chip On Board) construction.

In these embodiments, a semiconductor device having external electrodeshas been described, but a part of the substrate may be extended and usedfor external connection. A part of the substrate may be used as aconnector lead, connectors may be mounted on the substrate, or thesubstrate interconnect pattern itself may be connected to anotherelectronic instrument.

Furthermore, the formation of external connectors may be eliminated, andusing a solder cream applied on the motherboard at the time of mountingon the motherboard, external terminals may be formed as a result ofsurface tension during the fusion thereof. This semiconductor device isa so-called “land grid array” type of semiconductor device.

In FIG. 12 shows a circuit board 1000 on which the first embodiment ofthe semiconductor device 1 is mounted. For the circuit board 1000, anorganic substrate such as a glass epoxy substrate or the like isgenerally used. On the circuit board 1000, an interconnect pattern offor example copper is formed to constitute a desired circuit. Then bymechanical connection of corresponding parts of the interconnect patternand external electrodes 40 (see FIG. 1B) of the semiconductor device 1,electrical connection thereof is achieved.

It should be noted that the semiconductor device 1 has a mounting areawhich can be made as small as the area for mounting a bare chip, andtherefore by using this circuit board 1000 for an electronic instrument,the electronic instrument itself can be made more compact. Within thesame area, a larger mounting space can be obtained, and therefore higherfunctionality is possible.

Then as an electronic instrument equipped with this circuit board 1000,FIG. 13 shows a notebook personal computer 1100.

It should be noted that the above embodiments are examples of thepresent invention applied to a semiconductor device, but the presentinvention can be applied to any surface-mounted electronic componentrequiring a large number of external electrodes as in the case of asemiconductor device, whether an active component or passive component.As electronic components, for example, may be cited resistors,capacitors, coils, oscillators, filters, temperature sensors,thermistors, varistors, variable resistors, and fuses.

In all of the above-described embodiments, as the method of mounting thesemiconductor chip, face-down bonding is applied, but equally wirebonding, or TAB (Tape Automated Bonding), or similar mounting methodscan be applied. A mounted module type of semiconductor device in which acombination of the above-described semiconductor chips and electroniccomponents other than semiconductor chips is mounted may be configured.

What is claimed is:
 1. A semiconductor device comprising: a plurality ofsemiconductor chips having electrodes, and aligned in a horizontaldirection for face-down bonding; a substrate on which an interconnectpattern is formed, the interconnect pattern having bonding portions towhich the electrodes of the semiconductor chip are connected, and landsto which the bonding portions are electrically connected; and externalelectrodes provided on the lands, wherein the external electrodes aredisposed within a region where any one of the semiconductor chips ismounted; wherein the substrate is a flexible substrate and part of thesubstrate is bent; wherein a surface of the one semiconductor chip,which is disposed at a region where the external electrodes areprovided, opposite to a surface on which the electrodes are formed isattached to a surface of at least one remaining semiconductor chipopposite to a surface on which the electrodes are formed; and whereinthe substrate has at least one hole formed within a region to be bent.2. The semiconductor device as defined in claim 1, wherein the hole is aslot extending along a bending line; wherein the interconnect pattern isformed to pass over the hole; and wherein an edge of the slot extendingalong the bending line forms a part of an outer edge.
 3. Thesemiconductor device as defined in claim 1, wherein a plurality of theholes are formed; wherein the interconnect pattern is formed to passover the plurality of holes; and wherein the holes are slots extendingalong a bending line, and are aligned.
 4. The semiconductor device asdefined in claim 2, wherein a flexible resin is provided on theinterconnect pattern in the hole; and wherein the resin is bent togetherwith the substrate.
 5. A circuit board on which the semiconductor deviceas defined in claim 1 is mounted.
 6. An electronic instrument on whichthe circuit board as defined in claim 5 is mounted.
 7. A semiconductordevice comprising: a plurality of semiconductor chips having electrodes,and aligned in a horizontal direction for face-down bonding; a substrateon which an interconnect pattern is formed, the interconnect patternhaving bonding portions to which the electrodes of the semiconductorchip are connected, and lands to which the bonding portions areelectrically connected; and external electrodes provided on the lands,wherein the external electrodes are disposed within a region where anyone of the semiconductor chips is mounted; wherein the substrate is aflexible substrate and part of the substrate is bent; wherein a surfaceof the one semiconductor chip, which is disposed at a region where theexternal electrodes are provided, opposite to a surface on which theelectrodes are formed is attached to a surface of at least one remainingsemiconductor chip opposite to a surface on which the electrodes areformed; wherein the substrate has a slit formed within a region to bebent; and wherein the substrate is divided by the slit, and a gap isopened up between opposing divided edges.
 8. The semiconductor device asdefined in claim 7, wherein a joining member is provided spanning theslit.
 9. A circuit board on which the semiconductor device as defined inclaim 7 is mounted.
 10. An electronic instrument on which the circuitboard as defined in claim 9 is mounted.